Conventional semiconductor memory devices may use a memory structure characterized by a vertical stack of a tunnel oxide (e.g., SiO2), a polysilicon floating gate over the tunnel oxide, an interlayer dielectric over the floating gate, and a control gate over the interlayer dielectric. The vertical stack may be formed on a crystalline silicon substrate. The substrate may include a channel region positioned below the vertical stack and source and drain on opposing sides of the channel region.
Another type of memory cell structure is characterized by a vertical stack that includes an insulating tunnel oxide layer, a charge trapping nitride layer, an insulating top oxide layer, and a polysilicon control gate, all positioned on top of a crystalline silicon substrate. This particular structure of a silicon channel region, tunnel oxide, nitride, top oxide, and polysilicon control gate is often referred to as a SONOS (silicon-oxide-nitride-oxide-silicon) device. During fabrication of such memory devices, the charge trapping layer may become inadvertently charged, thereby shifting the threshold voltage to an undesirable level and potentially damaging the memory device. Thus, it would be desirable to provide an improved structure that eliminates this problem.